FIG. 1 is a block diagram of a conventional solid state imager 100, e.g. a CMOS imager. The imager 100 includes a plurality of pixels 102 for sensing a level of incident light. The pixels 102 are arranged into rows and columns to form a pixel array 101. Typically, each pixel 102 produces a reset signal Vrst and a photo signal Vsig onto a respective column line, which are sampled and held and then subtracted to remove common noise and provide an indication of the level of incident light seen by the pixel.
The imager 100 also includes a timing and control circuit 150 for controlling image acquisition and readout of the pixel array 101. The timing and control circuit 150 operates a row decoder 120, row driver 110, column decoder 170, a column memory 165, and a column parallel analog-to-digital converter 160. The row decoder 120 and row driver 110 are operated to select a row and supply operating signals to the selected row within the pixel array 101. The selected row is readout by the column parallel analog-to-digital converter 160, which has associated analog circuits for sampling and holding the Vrst and Vsig signals, and circuits for subtracting and amplifying the signals prior to amplification. These analog circuits receive signals from the pixels in the selected row via column readout lines. For each pixel 102 in the selected row, the analog circuits associated with analog-to-digital converter 160 subtracts the signals to form an analog pixel signal (either Vrst-Vsig or Vsig-Vrst). Also, the associated analog circuit may further amplify the signal or subject it to other form of analog processing. Finally, the column parallel analog-to-digital converter 160 converts the analog signal into digital form, which it stores in a column memory 165. The column memory 165 supplies the digital pixel values for a row of pixels in sequence to the image processor 180. Though not shown in FIG. 1, the digital signals may also bypass column memory 165 and be supplied directly to the image processor 180 from the column parallel analog-to-digital converter 160. The image processor 180 may perform additional processing operations on the digital signals such as, for example, color correction, demosaicing, defect correction, and others, before providing an image output. The output of the image processor 180 is routed to an output circuit 190, which can output the processed result to a storage device, screen, or printer.
Existing circuits for processing and digitizing the analog signals are relatively complex, particularly the analog-to-digital converter, making designs using existing circuits difficult to economically scale for large pixel arrays. Additionally, while pixel size continues to shrink, the associated analog-to-digital converters do not shrink at the same rate. The inherent minimum spacing required between analog-to-digital converters remains the same and becomes significant relative to pixel column width. The analog-to-digital converter layout becomes more complicated with increases in pixel array density and may lead to inefficient use of the design space. As analog-to-digital converters are made narrower to scale with shrinking pixel sizes, each converter's aspect ratio (the ratio of height to width) increases. This results in increased difficulties when laying out a circuit design. Accordingly, there is a need for a more space-efficient design for the converting of analog pixel signals to digital signals in solid-state imagers employing parallel columns for pixel signal readout.